Floating gate transistors

ABSTRACT

A floating gate MOS transistor comprises one or more control gates, an active channel, and at least one floating gate disposed between the control gate(s) and the active channel. First and second non-linear resistances couple the floating gate to first and second control voltage sources respectively, the non-linear resistances forming a voltage divider network which sets the operating voltage of the floating gate.

The present invention relates to floating gate transistors and moreparticularly to floating gate metal-oxide-semiconductor transistors.

Floating gate metal-oxide-semiconductor (AOS) transistors are deviceswith a first gate situated on a layer of insulating oxide directly abovethe transistor channel, and a second control gate situated on a layer ofinsulating oxide above the first gate. The first gate is electricallyisolated, hence the term ‘floating gate’, and any charge deposited onthe floating gate will be held almost indefinitely. Floating gatedevices are commonly used in digital integrated circuit (IC) design asthe storage components of FLASH EPROM. Typically, floating gate MOStransistors are fabricated using thin film technology, with a highdegree of integration between transistors and other components.

During the last decade, floating gate devices have also been exploitedin analogue IC design to implement circuits and small systems. Theavailability of a floating gate device, where the charge (or voltage) onthe floating gate can be controlled, leads to a number of useful circuitapplications, including:

-   -   Analogue memory: Floating gate devices can be used as ‘analogue        PROM’, particularly for applications such as neural networks        which require non-volatile analogue storage.    -   Tuning: Any charge stored on the floating gate will affect the        threshold voltage of the transistor. Thus transistors can        effectively be tuned to ensure their threshold voltages are        equal, by carefully controlling the charge stored on the        floating gate. A further example is the auto-zero floating gate        amplifier (AFGA), where the operating point at the input of the        amplifier can be set by tuning a floating gate structure.    -   Level shifting: The floating gate is also a level shifter.        Whatever charge is stored on the floating gate will add to the        voltage applied on the control gate. This level shifting may be        used (for example) for threshold shifting for tow-power low        voltage circuits. With a preset voltage offset, the functional        threshold of the transistor is changed accordingly.    -   Computation: The use of the floating gate transistor as a        computational element is very attractive for low power analogue        integrated circuit design. If the top (control) gate is divided        into a number of smaller gates with scaled areas, the floating        gate device effectively performs a weighted summation of the        voltages applied on each of these top gates. By scaling the top        gate areas (i.e. capacitor sizes) voltages can be weighted,        relative to the capacitor sizes. Such a structure is indicated        diagrammatically in FIG. 1. FIG. 1 a represents a stacked        floating gate device, where the top control gate (or gates) is        (or are) situated directly above the channel region of the        transistor. However such a stacked floating gate structure is        not recommended, as the process steps required to fabricate the        top gate can cause changes in the floating gate and substrate        which affect the transistor's threshold voltage. The preferred        architecture is shown in FIG. 1 b, where the floating gate is        extended laterally from the channel, and the top gate is        deposited over this extended region.

An informative review of both digital and analogue applications based onfloating gates can be found in: IEEE Transaction on Circuits andSystems—Part II, Special Issue on Floating Gate Circuits and Systems,January 2001.

Despite the obvious attractions, the usage of floating gate structuresin analogue circuits has not really taken off, due to a number ofpractical problems in the implementation of analogue floating gatecircuits. In particular, programming and control of the charge on thefloating gate is very difficult, and typically involves a combination ofFowler-Nordheim tunnelling and hot carrier injection. Both of theseprocesses typically require the application of large voltages whichallow electrons with sufficient energy to tunnel through the insulatingsilicon dioxide to and/or from the floating gate, thus altering the netcharge on the gate. Although this process is similar to the methods usedfor programming and erasing digital ROMs, repeated programming causesdegradation of the silicon oxide leading to transistor breakdown. Thisleads to long-term reliability problems for circuits which requireconstant tuning or alteration. In addition the application of highvoltages to perform tuning is itself undesirable.

Another problem with floating gate devices is that the long-term chargestorage capabilities are uncertain—over time the charge stored on thefloating gate may slowly leak away. This problem will only get worse asprocess dimensions shrink and the oxide thickness reduces. Any slightcharge leakage in a digital memory may not be a problem but is much moresignificant when an analogue value is being stored. This uncertainty inlong-term charge storage has contributed to the reluctance to exploitfloating gates in analogue ICs for commercial applications.

Recently, a mechanism for overcoming the above-mentioned problem infloating gate analogue circuit design—i.e. the difficulty inmanipulating the charge stored on the floating gate—was proposed at IEEEInt. Symposium on Circuits and Syst. (ISCAS) 2001, Pre-ConferenceWorkshops: ‘Multiple-Input Floating-Gate MOS Transistors as FunctionalDevices to Build Computing Circuits’ Tadashi Shibata, ‘Voltage-ModeFloating Gate Circuits’, Jaime Ramirez-Angulo. The mechanism involvesthe deliberate addition of a small leakage path to the floating gate(although in this architecture the gate is no longer truly “floating”,that terminology is still used for convenience). Such a leakage pathcould be provided using a high resistance value implemented usingconventional CMOS resistors. However, this would require a prohibitivelylarge silicon area, and thus is impractical. Shibata and Ramirez-Angulotherefore propose providing the leakage path via the addition of asingle pull-up reverse biased diode clamping the floating gate potentialto the positive supply rail, as shown in FIG. 2. The reverse-biaseddiode effectively acts as a very large resistor which pulls the voltageon the floating gate toward the voltage applied to the other end of thediode (in this case, the supply voltage). The voltage on the floatinggate will respond to voltages applied to the top gate(s), deviating fromthe voltage of the positive supply rail for as long as the gatevoltage(s) is(are) applied.

This simple mechanism, however, has severe limitations. Input signalperturbations of sufficient amplitude will forward bias the pull-updiode, introducing severe distortion into the device performance.Restricting the signal swing to well below one diode offset shouldreduce this effect, but the forward conduction problem can never beeliminated entirely.

It is an object of the present invention to overcome the abovedisadvantages.

According to a first aspect of the present invention there is provided afloating gate MOS transistor comprising:

-   -   one or more control gates;    -   an active channel;    -   at least one floating gate disposed substantially between the        control gate(s) and the active channel;    -   first and second non-linear resistances coupling the floating        gate to first and second control voltage sources respectively,        the resistances forming a voltage divider network which sets the        operating voltage of the floating gate.

The term “floating gate” is used here by convention, and indicates thatthe gate will provide floating gate functionality. The gate is not trulyfloating as it is coupled by the non-linear resistances to the voltagesources.

Providing that the non-linear resistances are sufficiently large invalue, leakage from the floating gate to the voltage sources isrelatively small. For short term fluctuations in the voltage(s) appliedto the control electrode(s), the floating gate acts as a true floatinggate.

In a preferred embodiment of the present invention, said non-linearresistances are provided by respective diodes, or transistors operatingas diodes, with the voltages applied to the first and second voltagesources being defined so that in use the diodes are reverse biased. Itwill be appreciated however that other means may be used to provide theresistances.

According to a second aspect of the present invention there is providedan electronic device comprising one or more floating gate transistorsaccording to the first aspect of the present invention.

In certain embodiments of the present invention, the electronic devicecomprises means for varying the voltage applied to one or both of thefirst and second control voltage sources. This allows the operatingvoltage of the floating gate to be tuned to an appropriate value.

According to a third aspect of the present invention there is provided amethod of operating the floating gate transistor of the first aspect ofthe invention, the method comprising applying first and second fixedvoltages to the first and second voltage sources respectively. Thefloating gate can be set to a desired operating voltage by anappropriate selection of the first and second voltages.

According to a fourth aspect of the present invention there is provideda method of operating the floating gate transistor of the first aspectof the invention, the method comprising applying first and secondvoltages to the first and second voltage sources respectively, at leastone of the first and second voltages being variable. The voltage atwhich the floating gate is operated can be set to a desired value bytuning one or both of the first and second voltages.

The use of a reverse biased diode to provide a high resistanceconnection between a floating gate and a control voltage source has thepotential drawback that it may take a relatively long time to charge thefloating gate to the operating voltage following, for example, power-up.

It is a further object to overcome this disadvantage, and to enable thefloating gate to charge to an operating voltage in a relatively shorttime.

According to a fifth aspect of the present invention there is provided afloating gate MOS transistor comprising:

-   -   one or more control gates;    -   an active channel;    -   at least one floating gate disposed substantially between the        control gate(s) and the active channel;    -   at least one resistance coupling the floating gate to a voltage        source, the resistance being provided by a MOS transistor having        its gate and source connected together, the transistor source        being coupled to said voltage source and the transistor drain        being coupled to the floating gate.

Preferably, the transistor gate is coupled to the transistor source viaa resistance. This resistance may be provided by a short length ofpolysilicon.

According to a sixth aspect of the present invention there is provided afloating gate MOS transistor comprising:

-   -   one or more control gates;    -   an active channel;    -   at least one floating gate disposed substantially between the        control gate(s) and the active channel;    -   an insulating region surrounding the floating gate or a contact        coupled to the floating gate; and    -   a conductor at least partially surrounding said insulating        region, wherein in use the conductor is coupled to an operating        voltage.

The insulating region will permit charge leakage from the floating gateto a very small extent. However, providing that this leakage issufficient, the floating gate will charge to the operating voltage. Theleakage through the insulating layer can be enhanced to a sufficientdegree by forming a contact on the floating gate, since the fabricationsteps contributing to the formation of this metal contact to thefloating gate cause impurities to damage the inter-oxide (insulating)layers, thus providing a mechanism for charge transport.

In one embodiment of the present invention, a metal contact is formed onthe floating gate, a charge leakage path extending between the metalcontact and said conductor. Preferably, the floating gate extendslaterally from above the active channel, and said metal contact isformed on the floating gate at the end of the gate remote from theactive channel. More preferably, said conductor surrounds an insulatingregion surrounding said metal contact and the adjacent portion of thefloating gate.

For a better understanding of the present invention and in order to showhow the same may be carried into effect reference will now be made, byway of example, to the accompanying drawings in which:

FIG. 1A illustrates schematically and in cross section a stackedfloating gate MOS transistor;

FIG. 1B illustrates schematically and in cross-section a floating gateMOS structure with the top gate offset from the channel;

FIG. 2 shows an equivalent circuit for a floating gate transistorincluding a prior art mechanism for setting the floating gate operatingvoltage;

FIG. 3 shows an equivalent circuit for a floating gate transistorincluding an improved mechanism for setting the floating gate operatingvoltage;

FIG. 4 shows a MOS transistor configuration for providing a resistancein the transistors of FIGS. 2 and 3;

FIG. 5 illustrates a known floating gate MOS transistor structure;

FIG. 6 a illustrates in plan view a floating gate transistor structurewith a deliberate leakage path introduced by the formation of a metalcontact to the floating gate;

FIG. 6 b illustrates in cross-section the floating gate transistorstructure of FIG. 6a;

FIG. 7 shows an equivalent circuit for the floating gate transistor ofFIG. 6;

FIG. 8 shows an equivalent circuit of an additive inverter constructedusing floating gate transistors; and

FIG. 9 shows an equivalent circuit of a biquadratic structure comprisingadditive inverters according to FIG. 8.

Prior art floating gate MOS transistors have been described above withreference to FIGS. 1 and 2. Whilst the architecture illustrated in FIG.2 provides an improvement over that of FIG. 1, that architecture is notideal because of limitations which it imposes on the voltage(s) whichcan be applied to the control gate(s).

An improvement to the architecture of FIG. 2 involves the use of tworeverse biased diodes (pn junctions) connected to the floating gate asshown in FIG. 3. These diodes can be connected directly to the powerrails V_(CC), V_(SS) which will thus set an operating point somewherebetween the two power supply rails. The diodes operate as non-linearresistances. By manipulating the relative diode dimensions, one of thediodes can be made ‘dominant’, thus defining the power rail which theoperating point will approach. Knowing the expected input voltage swing,the divider voltage may be set accordingly. Imposing a voltageperturbation on this structure within the expected limits should notforward bias the diodes. Thus compared to the single diode pull-up, thereverse diode voltage divider architecture will ensure a distortion freeoperation.

A more general solution is to use two separate tuning voltages connectedto the other terminals of the reverse-biased diodes, instead ofconnecting these points to the supply rails. The floating gate voltagewill then be determined by these tuning voltages, and effectively thiswill set the operating voltage of the transistors. This technique isgeneral and applicable both for analogue and digital circuits, and maybe implemented in any standard CMOS process. The penalty of course isextra connections and tuning voltages. An intermediate solution would beto have only one extra tuning voltage, and to connect the other diodeterminal to one of the supply rails.

A feature of the leaky floating gate approach is that very highresistance values are required to minimize the amount of leakage andensure that the device still behaves during normal operation as afloating gate structure. The downside of this is that devices using thismechanism possess long turn-on times during power up. Since the floatinggate capacitance must be charged up through the very high resistance,power-up times of the order of minutes may result. This is clearlyimpractical for many applications.

A proposed solution is to implement the reverse biased diode (leakyresistor) using a MOS transistor with gate-source shorted (see FIG. 4).In normal operation the transistor will be off, and the only currentflowing will be the leakage current of the drain diffusion (i.e. diodeleakage as desired). However at power-up the MOS transistor will quickly‘bootstrap’ the floating gate to the desired operating voltage, assumingthat during power-up the MOS gate potential rises more slowly than thesource potential. This situation is likely to occur since the gatecapacitance is much higher that the source capacitance, thus the gatepotential will automatically lag the source potential. However, toensure that this ‘bootstrap’ effect happens, the bootstrap MOS gateshould be connected to the positive supply rail through a length ofpolysilicon, which effectively implements a small resistor in serieswith the gate, thus further delaying the gate rise time. It will beappreciated that this shorted-gate MOS structure can be used both in thenovel architecture of FIG. 3 and in the prior art architecture of FIG.2, as well as in other floating gate MOS architectures.

In the circuits discussed above, reverse-biased diodes (and MOStransistors arranged to operate as diodes) are used to implement veryhigh resistance structures to ensure that the floating gates are madeonly very slightly leaky. Although reverse biased diodes offer largeresistance in a relatively small silicon area, they do not exhibit idealresistive behaviour (due e.g. to leakage currents).

It is known that in order to achieve good isolation, a floating gatemust be made as a single piece of polysilicon. If a metal contact isdeposited on top of the floating gate, the processing steps requiredcause changes in the oxide interface, allowing a small amount of chargetransport to occur. The nearest contact to this floating gate willcollect this charge, and thus the floating gate now has a direct leakagepath. Over time, the voltage on the floating gate will thus settle tothe potential on this nearby contact.

A solution proposed here is to exploit this (usually unwanted) effect bymaking a contact to the floating gate, thus “damaging” the surroundingoxide and introducing a transport path for electrons. The floating gateis then surrounded with a second contact which thus collects all of thefloating gate leakage charge which flows along the electron transport.Effectively, an ohmic contact to the floating gate is formed, theresistance being the very high resistance of the oxide interface layers.The surrounding contact is coupled to a voltage source, set to thedesired operating voltage.

The process steps for fabrication of a conventional floating gate devicewill vary depending on the process technology and production methods. Asimplified procedure which outlines in brief the main process steps forformation of the floating gate is as follows:

-   -   1. Thick field oxide is deposited and etched to define the        source, drain and channel regions. Thin gate oxide is deposited        over the whole device, and then etched away from source and        drain regions. Source and drain regions are diffused (n-type or        p-type implant for NMOS/PMOS devices respectively).    -   2. Polysilicon is deposited on top of the thin gate region        (self-aligned gate) to form the floating gate.    -   3. Field oxide and gate oxide layers are deposited to insulate        the floating gate.    -   4. Polysilicion for the second gate (control gate) is deposited        on top of the second thin gate oxide layer. Field oxide is then        deposited over the complete device, with windows being etched to        allow contact to the source, drain and control gates.

The basic device structure of such an NMOS floating gate device isillustrated in FIG. 5—note that dimensions are not to scale. FIG. 5shows a cross-sectional view of the transistor along the channel.

If a metal contact is made to the floating gate during the fabricationprocess, the fabrication procedure is now modified as follows:

-   -   1. Thick field oxide is deposited and etched to define the        source, drain and channel regions. Thin gate oxide is deposited        over the whole device, and then etched away from source and        drain regions. Source and drain regions are diffused (n-type or        p-type implant for NMOS/PMOS devices respectively).    -   2. Floating polysilicon gate deposited as before, but the gate        region is extended to allow additional area for metal contact to        be made.    -   3. Field and thin oxide layers are deposited, and etched to form        a window for the floating gate metal contact. The metal contact        is deposited, and covered with a further layer of thick oxide.        When a layer of silicon diode is deposited on top of an existing        layer, a solid insulator is form but with a minor systematic        “crack” between the layers. The etching process leaves        impurities along this interface, thus allowing a small amount of        charge transport to occur along this inter-dioxide layer.

A suitable layout for this architecture is shown schematically in FIG.6, with FIG. 6a showing a plan view and FIG. 6 b a cross-sectional view.Note that the cross section in FIG. 6 b is now perpendicular to thechannel (i.e. current in the channel flows into the plane of the paper).A ‘stand-alone’ metal contact is made to the floating gate. A diffusion(active) contact is made surrounding the floating gate. This secondcontact will collect most of the gate leakage charge since diffusioncontacts are deep, extending all the way down to the substrate. As shownin FIG. 6, it is impossible to enclose the floating gate contactcompletely. However, with the illustrated layout close to 80% of theedge should be controlled. The surrounding contact should be made asclose as possible to the floating gate in order to reduce the resistivevalue which otherwise might be too large even for floating gates.

Applying this structure to the leaky floating gate circuit will make theresulting circuit simpler since now only a single resistive connectionis required to the floating gate, as shown in FIG. 7.

This architectures described above are usable in both analogue anddigital circuits. In digital circuits an important use would be to allowthe tuning of threshold voltages of the transistors. Assuming alldevices are made with leaky gate structures, the thresholds of thedevices may be tuned to close to 0V allowing for much lower supplyvoltages. Supply voltages between 0.5-1 V have been demonstrated instandard high-threshold CMOS with more complicated, UV-based floatinggate tuning techniques. Many different kinds of gates may be designedand it is anticipated that the area-penalty for using these devices issmall. Device count is usually reduced, whilst stacked transistors maybe replaced with a single transistor having dual control gates.

In conventional digital logic, multiple input logic gates are formedtypically by vertically stacking a number of N and P-type transistors.The minimum supply voltage is thus limited by the need to providesufficient voltage headroom for these stacked devices. However by usingmultiple-input floating gate transistors we may reduce the stacking toonly two stacked transistors, one PMOS on top of one NMOS. The multipleinput logic gate functionality can then be implemented throughexploiting the multiple-input functionality of the floating gatetransistors. This allows very low supply voltages to be used.

In analogue circuits the leaky gate structures may be used in a numberof ways. Circuit biasing is simplified and the capacitive connectionsthrough a double poly capacitor enable an external operating voltage.Another property of floating-gate like structures is the perfect voltagesumming features. This summing structure could be used for mixingsignals. As with digital circuits, the threshold shifting ability isuseful for low power, low voltage analogue circuits. The free headroomtowards the rails may be regained, enabling a full rail-to-railoperation of circuits.

FIG. 8 illustrates an equivalent circuit for an additive inverter usingfloating gate transistors. The two-input additive inverter circuitfunctions as a standard one-input inverter except that it has anadditive property where the inverting threshold is given by the sum ofthe input voltages. The transconductance of the inverter can be tuned byvarying the offset voltage(s) of the floating gate transistor. If weconnect the output node to one of the inputs, and the couplingcapacitances are of equal sizes, the circuit behaves as an analoginverter, or analog inverting amplifier with gain=1.

FIG. 9 illustrates a biquadratic structure consisting of three identicaladditive inverters, each as illustrated in FIG. 8, and two filtercapacitors. The structure resembles a standard second order biquadstructure, except that the node voltage is inverted from the inputvoltage, and the output voltage is inverted from the node voltage. Whenthe output is fed back to the input inverter, the signal must beinverted. This is done by using an analog inverter coupling.

An example application of the technology described here is in the fieldof hearing aids. By cascading several second order biquads andseparately tuning the cutoff frequency and Q-factor of each stage, it ispossible to emulate the behavior of a human cochlea.

It will be appreciated by the person of skill in the art that variousmodifications may be made to the above described embodiments withoutdeparting from the scope of the present invention.

1. A floating gate MOS transistor comprising: one or more control gates;an active channel; at least one floating gate disposed substantiallybetween the control gate(s) and the active channel; first and secondnon-linear resistances coupling the floating gate to first and secondcontrol voltage sources respectively, the resistances forming a voltagedivider network which sets the operating voltage of the floating gate.2. A transistor according to claim 1, wherein said non-linearresistances are provided by respective diodes, or transistors operatingas diodes, with the voltages applied to the first and second voltagesources being defined so that in use the diodes are reverse biased. 3.An electronic device comprising one or more floating gate transistorsaccording to claim
 1. 4. An electronic device according to claim 3,wherein the electronic device comprises means for varying the voltageapplied to one or both of the first and second control voltage sourcesso that the operating voltage of the floating gate can be tuned to anappropriate value.
 5. A method of operating the floating gate transistorof claim 1, the method comprising applying first and second fixedvoltages to the first and second voltage sources respectively so as toset the floating gate to a desired operating voltage by an appropriateselection of the first and second voltages.
 6. A method of operating thefloating gate transistor of claim 1, the method comprising applyingfirst and second voltages to the first and second voltage sourcesrespectively, at least one of the first and second voltages beingvariable so that the voltage at which the floating gate is operated canbe set to a desired value by tuning one or both of the first and secondvoltages.
 7. A floating gate MOS transistor comprising: one or morecontrol gates; an active channel; at least one floating gate disposedsubstantially between the control gate(s) and the active channel; atleast one non-linear resistance coupling the floating gate to a voltagesource, the non-linear resistance being provided by a MOS transistorhaving its gate and source connected together, the transistor sourcebeing coupled to said voltage source and the transistor drain beingcoupled to the floating gate.
 8. A transistor according to claim 7, thetransistor gate being coupled to the transistor source via a resistance.9. A floating gate MOS transistor comprising: one or more control gates;an active channel; at least one floating gate disposed substantiallybetween the control gate(s) and the active channel; an insulating regionsurrounding the floating gate; and a conductor at least partiallysurrounding said insulating region, wherein in use the conductor iscoupled to an operating voltage.
 10. A transistor according to claim 9,wherein a metal contact is formed on the floating gate, a charge leakagepath extending between the metal contact and said conductor.
 11. Atransistor according to claim 10, wherein the floating gate extendslaterally from above the active channel, and said metal contact isformed on the floating gate at the end of the gate remote from theactive channel.
 12. A transistor according to claim 1 1, wherein saidconductor surrounds an insulating region surrounding said metal contactand the adjacent portion of the floating gate.
 13. An electronic devicecomprising one or more floating gate transistors according to claim 2.14. A method of operating the floating gate transistor of claim 2, themethod comprising applying first and second fixed voltages to the firstand second voltage sources respectively so as to set the floating gateto a desired operating voltage by an appropriate selection of the firstand second voltages.
 15. A method of operating the floating gatetransistor of claim 2, the method comprising applying first and secondvoltages to the first and second voltage sources respectively, at leastone of the first and second voltages being variable so that the voltageat which the floating gate is operated can be set to a desired value bytuning one or both of the first and second voltages.